Certain power supplies are subject to the safety regulations established by the Underwriters Laboratory (UL). In the United States, the UL1310 Class 2 standard, for example, limits the voltage, current, and power of each output of power supplies classified as Class 2 supplies. In Canada, UL requires that the open circuit voltage in certain power supplies be 42 volts or less for each output channel.
Power supplies often utilize two voltage conversion stages, i.e. a front end stage and an output stage. The front end stage may receive an input voltage, e.g. a 120VAC voltage, and convert the input voltage to a regulated DC output voltage. The output stage may receive the DC output of the front end stage and provide a regulated DC output using a DC/DC converter for each channel of the power supply. When a load is disconnected from a power supply, or when the load fails in a manner that establishes an open circuit, a relatively high voltage may be present at the output of the power supply. This voltage can provide a safety risk. To address this risk it is possible to limit the output voltage of a power supply when the power supply in an open circuit condition (i.e., when the load is removed or fails).
One known configuration for limiting per-channel open circuit output power and/or voltage of a power supply is illustrated in FIG. 4. The power supply circuit 1 shown in FIG. 4 includes a front end circuit 2, a controller circuit 4, a voltage converter circuit 6 including a switch controller 8, an output voltage protection circuit 10, and a current sense resistor Rsense. A light source 12 is coupled to output terminals 16, 18 of the power supply circuit 1. The front end circuit 2 receives an input voltage Vin and converts the input voltage to a regulated DC output voltage DCreg that is coupled to the voltage converter circuit 6. The voltage converter circuit 6 is configured as a known buck regulator circuit including a metal-oxide field effect transistor (MOSFET) QN which acts as a switch, the switch controller 8, a resistor RN, a diode DN, and an inductor LN. A source of the MOSFET QN is coupled to ground through the resistor RN, and a drain of the MOSFET QN is coupled to the high side of the regulated DC output voltage DCreg through the inductor LN and the parallel combination of the output voltage protection circuit 10 and the light source 12. The diode DN is coupled from the drain of the MOSFET QN to the high side of the regulated DC output voltage DCreg, and is reverse biased relative to the high side of the regulated DC output voltage DCreg. The switch controller 8 is coupled to a gate of the MOSFET QN for providing a pulse width modulated (PWM) gate drive signal to open and close the MOSFET QN in a known manner.
The controller circuit 4 is configured to provide an output to the switch controller 8 to enable and disable the PWM gate drive output of the switch controller 8 to the MOSFET QN. When the switch controller 8 is enabled by the output of the controller circuit 4, the PWM gate drive signal of the switch controller 8 drives the gate of the switch QN to place the switch QN in alternately conducting (“closed”) and non-conducing (“open”) states to provide a DC output voltage DCout to the light source 12 in a manner consistent with known buck converter configurations. When the switch controller 8 is disabled by the output of the controller circuit 4, the switch controller 8 places the MOSFET QN in a non-conducting (“open”) state, thereby disabling delivery of the DC output voltage DCout to the light source 12.
The output voltage protection circuit 10 includes a triac TN, a zener diode ZN, and a capacitor CN. As is known, a triac, such as the triac TN, conducts current in either direction between its terminals A1 and A2 when a triggering voltage greater than the voltage at the terminal A1 is applied to a gate G of the triac TN. In FIG. 4, the terminals A1 and A2 of the triac TN are coupled in parallel with the light source 12 across the output terminals 16, 18 of the power supply circuit 1. The capacitor CN is coupled between the inductor LN and the gate G of the triac TN at a node A, and the zener diode ZN is coupled between the node A and the high side of the regulated DC output voltage DCreg.
In operation, when an open circuit condition occurs at the output terminals 16, 18 of the power supply circuit 1, e.g. upon decoupling of the light source 12 from the output terminals 16, 18 or upon an open circuit failure of the light source 12, the high side of the regulated DC output voltage DCreg charges the capacitor CN through the Zener diode ZN. When the capacitor CN is charged to a voltage exceeding the trigger voltage of the triac TN, the triac TN conducts and establishes a short circuit across the output terminals 16, 18. In addition, when an open circuit occurs at the output terminals 16, 18 of the power supply circuit 1, current through the current sense resistor Rsense establishes a voltage Vsense at the input to the controller circuit 4 that causes the controller circuit 4 to disable the switch controller 8, thereby preventing delivery of the DC output voltage DCout to the output terminals 16, 18.